Due to its robustness and precision digital signal processing (DSP) has replaced analog signal processing (ASP) in most technical fields of today, which has enabled the development of information systems such as mobile communication systems and sophisticated medical aids etc. However, the real world is analog by nature, and there is therefore an increasing need for high performance analog-digital interfaces (ADI's), typically realized by a conventional analog-to-digital converter (ADC). Such ADCs are required in almost all signal processing and communication systems and they are often one of the most critical components, i.e., they tend to determine the overall system performance.
Analog-to-digital conversion can be viewed as a uniform sampling followed by a quantization (truncating or rounding the value). The resolution of an ADC is the number of bits used in the quantization and the data rate of an ADC is the number of samples produced per second on average. Hence, a sampling period of e.g. T gives a data rate or sampling rate of 1/T.
FIGS. 1a and 1b illustrate an exemplifying analog-to-digital conversion wherein a sequence X(n) is obtained from an analog signal Xa(t) by sampling the latter equidistantly at t=nT, i.e., X(n)=Xa(nT), followed by quantization.
There are several existing analog-to-digital conversion techniques, which can be grouped into categories such as flash, pipelined, successive-approximation, integrating, and oversampling sigma-delta converters. The ADC performance is mainly described in terms of sampling rate, resolution, and power consumption.
Previously, ADCs have been good enough for their purposes, but their limitations are now becoming problematic since their capacity does no longer match the rapid development of digital technology. The situation is getting worse as semiconductor process feature sizes are decreasing and data rate requirements of information processing systems increase, since for ADCs, the achievable resolution is highly dependent on the conversion rate. Initially, the progress in analog-to-digital converter development was due to new and better analog circuit topologies and technologies. However, during the past decade, it has become evident that additional major performance improvements most likely cannot be achieved by further progress in topologies and technologies alone. For example, during the last decade, only some 1.5-2 bits of resolution improvement has been achieved for a given speed performance.
In all ADC architectures and technologies known today it is very difficult to simultaneously achieve high resolution and high sampling rate. Such speed/resolution trade-offs are very common in analog circuit design. Resolution is to a large extent determined by matching accuracy of physical devices. For example, in Metal-Oxide Semiconductor (MOS) technology, the variance of the matching error of two devices is a function of the inverse of the device area. Hence, when increasing the area the matching will be improved and the accuracy is increased. However, increasing the area also increases parasitic capacitances of the devices which in general decreases the operational bandwidth of the circuit and thereby reduces the speed.
One technique, used since the early eighties, aimed to overcome the speed limitation of high-resolution analog-to-digital conversion is the operation of several ADCs in parallel. The overall ADC system may consists of, say, N ADCs. This channelization into N branches enables a reduction of the sampling frequency of each individual converter. Hence, if an effective sampling rate fs is required, each ADC can work at the reduced sampling frequency fs/N. The sampling instants are distributed uniformly in time according to tk=(k+mN)T, k=0, 1, . . . N-1, and T=1/fs i.e., the converters are time-interleaved. The principle of ideal N time-interleaved ADCs is shown in FIGS. 2a and 2b. 
Using a group of identical ADCs (the ideal case), which is the most commonly selected scheme, the resolution of the overall time-interleaved ADC system is equal to that of each individual converter. In view of the speed/resolution trade-off, the reduction in sampling rate of each converter used in a time-interleaved ADC enables the realization of a higher resolution than what would be possible if a single ADC was to be used.
Similarly, if each ADC is being operated at the limit of its speed, the overall ADC sampling rate can be increased beyond what is achievable using a single unit.
However, there are significant problems associated with time-interleaved ADCs. Besides performance degrading effects common to all ADCs, such as for example random variations to the location of the sampling instants (sampling jitter), sample-and-hold circuit nonlinearity, comparator metastability, and nonuniform quantization (static nonlinearity), new errors limit the achievable resolution. The former degradations are consequences of fundamental and inevitable error sources such as fabrication process imperfections, non-symmetric circuit layout, circuit parasitics, and noise. The new errors arise from the parallelization itself and are all introduced by differences between the individual ADCs used in the time-interleaved ADC system. These errors are referred to as channel mismatch errors, and give rise to nonlinear distortion that degrades the resolution.
As seen in FIG. 2, the subconverters in a time-interleaved ADC system are operated periodically and each ADC is responsible for the task of digitizing every Nth sample. Comparing with the desired behavior of a single ADC, as illustrated in FIGS. 1a and 1b, one can see that in order to work properly, a time-interleaved ADC system requires that all sub-converters behave identically. If not, the system will not be equivalent to one single ADC working at N times higher sampling frequency.
One channel mismatch error originates from discrepancies in the time instants when each sub-converter is actually taking samples from the analog waveform, i.e. the aperture delay mismatch. Aperture delay of an ADC is the time difference between when a sample is supposed to be taken and when the sample is actually taken. In an ADC, the aperture delay varies slightly from sample to sample and this variation is called aperture jitter. The aperture jitter of an ADC is, however, in general much shorter than the average aperture delay. Aperture jitter is present in all types of ADCs and is hence not an error specific to time-interleaved ADCs. We will, therefore, not consider the aperture jitter further, but instead focus on the average aperture delay and the damage the average aperture delay of the sub-converters causes to a system of time-interleaved ADCs.
Other harmful channel mismatch errors are first-order gain mismatch and offset mismatch. Like the aperture delay mismatches the distortion caused by these errors must also be eliminated or at least reduced to a satisfactory level.
In order to remove these mismatch errors, the errors between the different ADC:s must first be determined. These errors can then be used to o remove the errors from the digitized signal.
One approach to determine the timing errors in particular is to apply a known calibration signal, and compare the resulting digitized signal with the expected result. An example of this approach is given in the journal paper “A digital-background calibration technique for minimizing timing-error effects in time-interleaved ADC's” by H. Jin and E. K. F. Lee. However, such an approach requires careful timing of input and output, in order to enable a correct comparison, and this makes the method very difficult to implement with high precision.
Instead, it has been proposed to estimate the timing errors from an unknown, but bandlimited signal. One example of such estimation in a parallel ADC is given in WO 04/079917. In the system described in WO 04/079917, the digitized signal can be used to estimate the timing errors, as long as it is band limited to the system bandwidth. However, this requires feedback of the reconstructed signal to the estimator, so that each iteration of the timing error estimation is based on the current reconstruction.
Considering the drawbacks affecting the prior art time-interleaved ADCs it is an object of the present invention to provide estimation of mismatch errors with such precision that no feedback of the reconstructed signal is required. It is a further object to enable reconstruction of a digitized signal by means of an unknown bandlimited signal.